1. Technical Field
The present disclosure relates to filtering the input/output (I/O) of a Field Programmable Gate Array (FPGA), and more specifically to adding a logic layer between the FPGA I/O and the core logics of the FPGA.
2. Introduction
FPGAs are integrated circuits which can be configured by users after manufacturing. Each FPGA contains I/O (generally in the form of pins), programmable logic blocks, and programmable routing which connects the logic blocks to one another and the I/O. Users develop FPGA logic programming codes using a Hardware Description Language, such as VHDL or Verilog, use EDA (Electronic Design Automation) tools to compile and synthesize the codes into FPGA programming specific to an FPGA, and then upload that program into the FPGA for implementation. To verify the FPGA codes are operating correctly, users apply known inputs to the appropriate pins of the FPGA and compare resulting outputs to desired outputs, either in a simulation environment or in a live system.